The wide acceptance and current popularity of data transmission is evidenced by the proliferation of digital peripheral equipment which is connectable to computer processors or the like. In transmitting data from one piece of equipment to another, such transmission often requires communication between extremely fast operating equipment such as processors, and other slower operating peripheral equipment such as disk storage systems and printers.
The most efficient use of such a system is realized when the various interconnected components of the system can communicate asynchronously, so that the fast operating equipment need not be delayed in order to communicate with slow peripheral equipment, such as a printer.
It is a well-known practice to employ memories as intermediate buffers between the components of the system for storing data written therein by the transmitting equipment at one speed and read therefrom by destination equipment at another speed. With this arrangement it is imperative that memory storage space is available when the transmitting equipment transmits data. Moreover when the memory storage space is full, it is necessary that the transmitting equipment be signaled so that further transmission cannot be accomplished. It is equally important that the destination equipment be signaled by the intermediate buffer when the memory storage is empty so that further reading thereof cannot be accomplished until additional data has been written therein by the transmitting equipment.
In the past, such requirements have been met by shift registers that serially write digital words therein at a desired speed and read serially therefrom at a different speed. Such devices are of limited storage and have unacceptable delay times. More recently, random access memories have been developed which have a First In First Out (FIFO) characteristic. These memories can be quickly accessed to read out the oldest data stored in the memory. The movement of data within such a memory is managed by a control section which maintains an account of which storage cells
hold effective data. See, for example, U.S. Pat. Nos. 4,151,068 and 4,459,681.
Such asynchronous FIFO memories are normally equipped with status flag circuitry to detect various degrees of fullness of the memory array including EMPTY, FULL, HALF-FULL and various other fractions of the total memory capacity. However, there is often a need for a status flag to detect degrees of fullness other than these fixed fractions. As such, the users frequently desire the status flags that can be programmed and reprogrammed into the FIFO.
However, the status flags of such FIFOs and status flag circuitry have encountered problems. One type of circuitry uses binary counters connected to read and write clocks (READ CLK; WRITE CLK) and also connected to binary adders and subtractors. The binary adders or subtractors detect differences between read and write addresses as such READ and WRITE CLK pulses are counted. These adders and subtractors are relatively large circuits and usually are slow to generate status signals. As such, the entire system has to be slowed down to account for the speed of the component adders and subtractors. Also, when multiple outputs switch on binary counters, particularly in opposite directions, momentary false output results appear thus requiring even more time for the system to wait for the output results to stabilize. A further problem with such prior art devices is that they require additional circuitry to generate status flags and such additional circuitry often requires counter outputs, control signals, etc. to arrive at precisely controlled times in relation to each other. In an integrated circuit environment, such coordination of timing and control signals is quite difficult to achieve due to the wide range of operating conditions and processing variations.
As such, there has arisen a need for a FIFO that has programmable status flags and who's operation is immune from different operating conditions and process variations.